1. Field of the Invention
The present invention relates to a sampling and holding (S/H) circuit, and more particularly, to a positive/negative S/H circuit that synchronously outputs positive/negative S/H results.
2. Description of the Prior Art
Sampling and holding (S/H) circuits for traditional touch panels usually operate on only positive or negative clock cycles, thus 50% of the clock cycle is wasted. Alternatively, some S/H circuits employ inverters so that they are able to operate on both positive and negative clock cycles (e.g. negative pulses are converted into positive pulses, so that a S/H circuit that operates only on positive clock cycles is able to operate on what were originally negative clock cycles). However, transmission time delay of the inverters may cause pulse overlap in high-speed S/H circuits (e.g. assuming a negative pulse is converted into a positive pulse by an inverter and a 5% transmission time delay is introduced, then 5% of pulse time at the end of the waveform of this positive pulse will overlap with 5% of pulse time at the beginning of the waveform of the next positive pulse), such clock overlapping issue is even more prominent in high-frequency S/H circuits or inverters with larger transmission time delays. This causes disorder in operations of the S/H circuits.
Alternatively, some S/H circuits use inverters to perform direct phase conversion on the results sampled and held during positive clock cycles and then output the converted results. As such, positive/negative S/H results can be outputted, but transmission time delay in the inverters may cause the converted results to be outputted slower, so this output method is not synchronous, and in high-speed S/H circuits, signal waiting times of subsequent circuits are also prolonged.
From the above shortcomings, the present invention provides a positive/negative S/H circuit that solves the asynchronous output problem for positive/negative sampling results of the prior-art S/H circuits.